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| author | Zachary Snow <zach@zachjs.com> | 2021-03-03 14:36:19 -0500 |
|---|---|---|
| committer | Zachary Snow <zachary.j.snow@gmail.com> | 2021-03-06 15:20:34 -0500 |
| commit | b1a8e73a609d3065f1caf7a230529443b54295bc (patch) | |
| tree | e682f44ba07bf036005113e0dc5def403e8dc163 /tests/verilog/absurd_width_const.ys | |
| parent | d245e2bae59d18eb641aa6b324eef1bbbfa13c38 (diff) | |
| download | yosys-b1a8e73a609d3065f1caf7a230529443b54295bc.tar.gz yosys-b1a8e73a609d3065f1caf7a230529443b54295bc.tar.bz2 yosys-b1a8e73a609d3065f1caf7a230529443b54295bc.zip | |
sv: fix some edge cases for unbased unsized literals
- Fix explicit size cast of unbased unsized literals
- Fix unbased unsized literal bound directly to port
- Output `is_unsized` flag in `dumpAst`
Diffstat (limited to 'tests/verilog/absurd_width_const.ys')
0 files changed, 0 insertions, 0 deletions