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| author | whitequark <whitequark@whitequark.org> | 2021-02-04 09:57:28 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-02-04 09:57:28 +0000 |
| commit | baf1875307f1608762169d3037ba005da88b201e (patch) | |
| tree | 44b84ab2ef42251cdc916a417e105c3f172c2a19 /tests/verilog/bug656.v | |
| parent | afcc31ceba35d33fc11f9e1592956bb4112ca0e3 (diff) | |
| parent | fe74b0cd95267bc78953236311382653a6db7f60 (diff) | |
| download | yosys-baf1875307f1608762169d3037ba005da88b201e.tar.gz yosys-baf1875307f1608762169d3037ba005da88b201e.tar.bz2 yosys-baf1875307f1608762169d3037ba005da88b201e.zip | |
Merge pull request #2529 from zachjs/unnamed-genblk
verilog: significant block scoping improvements
Diffstat (limited to 'tests/verilog/bug656.v')
| -rw-r--r-- | tests/verilog/bug656.v | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/tests/verilog/bug656.v b/tests/verilog/bug656.v new file mode 100644 index 000000000..068d045fd --- /dev/null +++ b/tests/verilog/bug656.v @@ -0,0 +1,21 @@ +module top #( + parameter WIDTH = 6 +) ( + input [WIDTH-1:0] a_i, + input [WIDTH-1:0] b_i, + output [WIDTH-1:0] z_o +); + genvar g; + generate + for (g = 0; g < WIDTH; g = g + 1) begin + if (g > 2) begin + wire tmp; + assign tmp = a_i[g] || b_i[g]; + assign z_o[g] = tmp; + end + else begin + assign z_o[g] = a_i[g] && b_i[g]; + end + end + endgenerate +endmodule |