diff options
| author | Zachary Snow <zach@zachjs.com> | 2021-02-26 18:08:23 -0500 |
|---|---|---|
| committer | Zachary Snow <zach@zachjs.com> | 2021-02-26 18:08:23 -0500 |
| commit | bbff844acd15c274a6619050d1251aea4698ef56 (patch) | |
| tree | 9d1532428e3b5e587a014ed4d66e2e9cbcd364ab /tests/verilog/conflict_memory_wire.ys | |
| parent | dcd9f0af23f9b580b044890452ecf1aef59bbb85 (diff) | |
| download | yosys-bbff844acd15c274a6619050d1251aea4698ef56.tar.gz yosys-bbff844acd15c274a6619050d1251aea4698ef56.tar.bz2 yosys-bbff844acd15c274a6619050d1251aea4698ef56.zip | |
genrtlil: improve name conflict error messaging
Diffstat (limited to 'tests/verilog/conflict_memory_wire.ys')
| -rw-r--r-- | tests/verilog/conflict_memory_wire.ys | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/tests/verilog/conflict_memory_wire.ys b/tests/verilog/conflict_memory_wire.ys new file mode 100644 index 000000000..5c296074f --- /dev/null +++ b/tests/verilog/conflict_memory_wire.ys @@ -0,0 +1,7 @@ +logger -expect error "Cannot add memory `\\x' because a signal with the same name was already created" 1 +read_verilog <<EOT +module top; + reg [2:0] x; + reg [2:0] x [0:0]; +endmodule +EOT |