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| author | whitequark <whitequark@whitequark.org> | 2021-03-01 08:10:19 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-03-01 08:10:19 -0800 |
| commit | ca5f5ffcd63bc18a5e0ae1bdb1065f148ce3c4da (patch) | |
| tree | d6fb01c328a9da739b2f2c0b448fe47791258e5d /tests/verilog/conflict_wire_memory.ys | |
| parent | 0fb4224ebca86156a1296b9210116d9a9cbebeed (diff) | |
| parent | bbff844acd15c274a6619050d1251aea4698ef56 (diff) | |
| download | yosys-ca5f5ffcd63bc18a5e0ae1bdb1065f148ce3c4da.tar.gz yosys-ca5f5ffcd63bc18a5e0ae1bdb1065f148ce3c4da.tar.bz2 yosys-ca5f5ffcd63bc18a5e0ae1bdb1065f148ce3c4da.zip | |
Merge pull request #2615 from zachjs/genrtlil-conflict
genrtlil: improve name conflict error messaging
Diffstat (limited to 'tests/verilog/conflict_wire_memory.ys')
| -rw-r--r-- | tests/verilog/conflict_wire_memory.ys | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/tests/verilog/conflict_wire_memory.ys b/tests/verilog/conflict_wire_memory.ys new file mode 100644 index 000000000..77520fea9 --- /dev/null +++ b/tests/verilog/conflict_wire_memory.ys @@ -0,0 +1,7 @@ +logger -expect error "Cannot add signal `\\x' because a memory with the same name was already created" 1 +read_verilog <<EOT +module top; + reg [2:0] x [0:0]; + reg [2:0] x; +endmodule +EOT |