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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2022-02-12 11:35:10 +0100 |
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| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2022-02-12 11:48:57 +0100 |
| commit | 3a62fa0c97446f0b904f57751c0325e84c9ff3ab (patch) | |
| tree | 71c6ed72608bde35582edc5b07b43a23437b2a72 /tests/verilog/delay_time_scale.ys | |
| parent | 1772a1e98eb7c659d070d62ff745c506cbd41f8b (diff) | |
| download | yosys-3a62fa0c97446f0b904f57751c0325e84c9ff3ab.tar.gz yosys-3a62fa0c97446f0b904f57751c0325e84c9ff3ab.tar.bz2 yosys-3a62fa0c97446f0b904f57751c0325e84c9ff3ab.zip | |
gowin: Add remaining block RAM blackboxes.
Diffstat (limited to 'tests/verilog/delay_time_scale.ys')
0 files changed, 0 insertions, 0 deletions