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author | Zachary Snow <zach@zachjs.com> | 2021-12-30 00:06:23 -0700 |
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committer | Zachary Snow <zachary.j.snow@gmail.com> | 2022-01-03 08:17:46 -0700 |
commit | 207af4196b588546344db80df6cb3f77df784aaf (patch) | |
tree | 8f4ae57445302ca436d6da91c5ef9b0d3009ab00 /tests/verilog/doubleslash.ys | |
parent | 8c509a5659d540dc41f6cc19ee6989fc249f519d (diff) | |
download | yosys-207af4196b588546344db80df6cb3f77df784aaf.tar.gz yosys-207af4196b588546344db80df6cb3f77df784aaf.tar.bz2 yosys-207af4196b588546344db80df6cb3f77df784aaf.zip |
fixup verilog doubleslash test
- add generated doubleslash.v to .gitignore
- ensure backend verilog can be read again
Diffstat (limited to 'tests/verilog/doubleslash.ys')
-rw-r--r-- | tests/verilog/doubleslash.ys | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/tests/verilog/doubleslash.ys b/tests/verilog/doubleslash.ys index 8a51f12c2..c41673ee5 100644 --- a/tests/verilog/doubleslash.ys +++ b/tests/verilog/doubleslash.ys @@ -17,3 +17,5 @@ proc opt -full write_verilog doubleslash.v +design -reset +read_verilog doubleslash.v |