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| author | whitequark <whitequark@whitequark.org> | 2021-02-23 21:46:16 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-02-23 21:46:16 +0000 |
| commit | ad2960adb7ae66d524e4ac5f8f5c16cbca3730e2 (patch) | |
| tree | 7da8cbbf621850924cee90e94d8ad95597f2fa5c /tests/verilog/func_arg_mismatch_4.ys | |
| parent | 4b31223e60f8854d50c1d1bbddca528fbf37d261 (diff) | |
| parent | b6af90fe20bc92631061c48c328f3c6e4760e4df (diff) | |
| download | yosys-ad2960adb7ae66d524e4ac5f8f5c16cbca3730e2.tar.gz yosys-ad2960adb7ae66d524e4ac5f8f5c16cbca3730e2.tar.bz2 yosys-ad2960adb7ae66d524e4ac5f8f5c16cbca3730e2.zip | |
Merge pull request #2594 from zachjs/func-arg-width
verilog: fix sizing of constant args for tasks/functions
Diffstat (limited to 'tests/verilog/func_arg_mismatch_4.ys')
| -rw-r--r-- | tests/verilog/func_arg_mismatch_4.ys | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/tests/verilog/func_arg_mismatch_4.ys b/tests/verilog/func_arg_mismatch_4.ys new file mode 100644 index 000000000..87ec1c299 --- /dev/null +++ b/tests/verilog/func_arg_mismatch_4.ys @@ -0,0 +1,12 @@ +logger -expect error "Incompatible re-declaration of constant function wire" 1 +read_verilog -sv <<EOT +module top; + function automatic integer f; + input [1:0] inp; + integer inp; + f = inp; + endfunction + integer x; + initial x = f(0); +endmodule +EOT |