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| author | Zachary Snow <zach@zachjs.com> | 2022-05-30 16:45:39 -0400 |
|---|---|---|
| committer | Zachary Snow <zach@zachjs.com> | 2022-05-30 16:45:39 -0400 |
| commit | a650d9079fa4732a6d118f2764d5abc2522a6b37 (patch) | |
| tree | 5d4e92924a37dd9f358692d98180e43d71d6d95c /tests/verilog/func_tern_hint.ys | |
| parent | cea7e85d607304faf36779757df14b4445fe1cfe (diff) | |
| download | yosys-a650d9079fa4732a6d118f2764d5abc2522a6b37.tar.gz yosys-a650d9079fa4732a6d118f2764d5abc2522a6b37.tar.bz2 yosys-a650d9079fa4732a6d118f2764d5abc2522a6b37.zip | |
verilog: fix width/sign detection for functions
Diffstat (limited to 'tests/verilog/func_tern_hint.ys')
| -rw-r--r-- | tests/verilog/func_tern_hint.ys | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/tests/verilog/func_tern_hint.ys b/tests/verilog/func_tern_hint.ys new file mode 100644 index 000000000..ab8a1e032 --- /dev/null +++ b/tests/verilog/func_tern_hint.ys @@ -0,0 +1,4 @@ +read_verilog -sv func_tern_hint.sv +proc +opt +sat -verify -seq 1 -prove-asserts -show-all |