diff options
| author | Zachary Snow <zach@zachjs.com> | 2023-02-12 17:03:37 -0500 |
|---|---|---|
| committer | Zachary Snow <zach@zachjs.com> | 2023-02-12 17:03:37 -0500 |
| commit | 26a6c604788f947df5142088224b1989320ba467 (patch) | |
| tree | b3da0b577aa2ecc561a8a0478fb309a46e56bc66 /tests/verilog/gen_block_end_label_wrong.ys | |
| parent | 5ea2c290a58dcc2a2eacacd8b3288d9a1d7037bb (diff) | |
| download | yosys-26a6c604788f947df5142088224b1989320ba467.tar.gz yosys-26a6c604788f947df5142088224b1989320ba467.tar.bz2 yosys-26a6c604788f947df5142088224b1989320ba467.zip | |
Add test for typenames using constants shadowed later on
This possible edge case came up while reviewing #3555. It is currently
handled correctly, but there is no clear test coverage.
Diffstat (limited to 'tests/verilog/gen_block_end_label_wrong.ys')
0 files changed, 0 insertions, 0 deletions