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| author | Jannis Harder <me@jix.one> | 2023-02-10 16:06:16 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-02-10 16:06:16 +0100 |
| commit | f3c4e93d2499dd96e331e49ad09540af9b9cd0bd (patch) | |
| tree | accfcd085e6df82ac6a54331048bdbc716f1a1e0 /tests/verilog/gen_block_end_label_wrong.ys | |
| parent | b1a011138ccc7ac840806d2a787f48f6baf6f107 (diff) | |
| parent | d31d5da69ff3fa956161cbaf5553951394700108 (diff) | |
| download | yosys-f3c4e93d2499dd96e331e49ad09540af9b9cd0bd.tar.gz yosys-f3c4e93d2499dd96e331e49ad09540af9b9cd0bd.tar.bz2 yosys-f3c4e93d2499dd96e331e49ad09540af9b9cd0bd.zip | |
Merge pull request #3667 from jix/xprop-test-make-fix
tests: in xprop tests, use MAKE variable if set
Diffstat (limited to 'tests/verilog/gen_block_end_label_wrong.ys')
0 files changed, 0 insertions, 0 deletions