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| author | Zachary Snow <zach@zachjs.com> | 2021-02-05 19:38:10 -0500 |
|---|---|---|
| committer | Zachary Snow <zach@zachjs.com> | 2021-02-05 19:51:30 -0500 |
| commit | 4b2f97733104c4e68dfdb0d89c1b03da137010c4 (patch) | |
| tree | 6f79a19d87ca4e717bf171b9183884f0c3d0682f /tests/verilog/genblk_port_decl.ys | |
| parent | 3d9898272a5afd60f6080603bf065056d9dca000 (diff) | |
| download | yosys-4b2f97733104c4e68dfdb0d89c1b03da137010c4.tar.gz yosys-4b2f97733104c4e68dfdb0d89c1b03da137010c4.tar.bz2 yosys-4b2f97733104c4e68dfdb0d89c1b03da137010c4.zip | |
genrtlil: fix signed port connection codegen failures
This fixes binding signed memory reads, signed unary expressions, and
signed complex SigSpecs to ports. This also sets `is_signed` for wires
generated from signed params when -pwires is used. Though not necessary
for any of the current usages, `is_signed` is now appropriately set when
the `extendWidth` helper is used.
Diffstat (limited to 'tests/verilog/genblk_port_decl.ys')
0 files changed, 0 insertions, 0 deletions