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| author | Zachary Snow <zach@zachjs.com> | 2021-05-26 18:22:31 -0400 |
|---|---|---|
| committer | Zachary Snow <zachary.j.snow@gmail.com> | 2021-06-08 15:02:57 -0400 |
| commit | c79fbfe0a130f1a2979413174c3e5688433bafe3 (patch) | |
| tree | 4779bf4befa1f9459d96566a3ff70af287bb5aa4 /tests/verilog/mem_bounds.sv | |
| parent | d9f11bb7a631ad309b9328d33b2f41a4987b6222 (diff) | |
| download | yosys-c79fbfe0a130f1a2979413174c3e5688433bafe3.tar.gz yosys-c79fbfe0a130f1a2979413174c3e5688433bafe3.tar.bz2 yosys-c79fbfe0a130f1a2979413174c3e5688433bafe3.zip | |
mem2reg: tolerate out of bounds constant accesses
This brings the mem2reg behavior in line with the nomem2reg behavior.
Diffstat (limited to 'tests/verilog/mem_bounds.sv')
| -rw-r--r-- | tests/verilog/mem_bounds.sv | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/tests/verilog/mem_bounds.sv b/tests/verilog/mem_bounds.sv new file mode 100644 index 000000000..7fb2fb042 --- /dev/null +++ b/tests/verilog/mem_bounds.sv @@ -0,0 +1,27 @@ +module top; + reg [0:7] mem [0:2]; + + initial mem[1] = '1; + wire [31:0] a, b, c, d; + assign a = mem[1]; + assign b = mem[-1]; + assign c = mem[-1][0]; + assign d = mem[-1][0:1]; + + always @* begin + + assert ($countbits(a, '0) == 24); + assert ($countbits(a, '1) == 8); + assert ($countbits(a, 'x) == 0); + + assert ($countbits(b, '0) == 24); + assert ($countbits(b, 'x) == 8); + + assert ($countbits(c, '0) == 31); + assert ($countbits(c, 'x) == 1); + + assert ($countbits(d, '0) == 30); + assert ($countbits(d, 'x) == 2); + + end +endmodule |