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authorClaire Xen <claire@clairexen.net>2022-02-11 16:03:12 +0100
committerGitHub <noreply@github.com>2022-02-11 16:03:12 +0100
commit49545c73f7f5a5cf73d287fd371f2ff39311f621 (patch)
treed0f20b8def36e551c6735d4fc6033aaa2633fe80 /tests/verilog/package_task_func.sv
parent90b40aa51f7d666792d4f0b1830ee75b81678a1f (diff)
parente0165188669fcef2c5784c9916683889a2164e5d (diff)
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Merge branch 'master' into clk2ff-better-names
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diff --git a/tests/verilog/package_task_func.sv b/tests/verilog/package_task_func.sv
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+package P;
+ localparam Y = 2;
+ localparam X = Y + 1;
+ task t;
+ output integer x;
+ x = Y;
+ endtask
+ function automatic integer f;
+ input integer i;
+ f = i * X;
+ endfunction
+ function automatic integer g;
+ input integer i;
+ g = i == 0 ? 1 : Y * g(i - 1);
+ endfunction
+ localparam Z = g(4);
+endpackage
+
+module top;
+ integer a;
+ initial P::t(a);
+ integer b = P::f(3);
+ integer c = P::g(3);
+ integer d = P::Z;
+
+ assert property (a == 2);
+ assert property (b == 9);
+ assert property (c == 8);
+ assert property (d == 16);
+endmodule