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| author | whitequark <whitequark@whitequark.org> | 2021-03-01 22:46:07 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-03-01 22:46:07 -0800 |
| commit | 375af199ef4df45ccf02c66e0171b4282c6cf1eb (patch) | |
| tree | 18e54f4b88b8cb4639da0a1d688d07200bacec3b /tests/verilog/param_no_default_unbound_1.ys | |
| parent | 0e0f84299a4ae4d0a312c33039378e1ebb20709d (diff) | |
| parent | 10a6bc9b81d1c2236e80a608778c904aebe54c28 (diff) | |
| download | yosys-375af199ef4df45ccf02c66e0171b4282c6cf1eb.tar.gz yosys-375af199ef4df45ccf02c66e0171b4282c6cf1eb.tar.bz2 yosys-375af199ef4df45ccf02c66e0171b4282c6cf1eb.zip | |
Merge pull request #2620 from zachjs/port-int-types
verilog: fix sizing of ports with int types in module headers
Diffstat (limited to 'tests/verilog/param_no_default_unbound_1.ys')
0 files changed, 0 insertions, 0 deletions