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| author | whitequark <whitequark@whitequark.org> | 2021-01-25 10:36:07 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-01-25 10:36:07 +0000 |
| commit | ffbd813a8c640f5653a0b8e9f54acbe398c2cf2e (patch) | |
| tree | d980214299059206316ef11a904f050c15d0f1ed /tests/verilog/task_attr.ys | |
| parent | 410ea422429aa31e5b5af7628d6126a3d3884512 (diff) | |
| parent | 4fadcc8f25d5ef1e494aa7d5e49d893afdaa1705 (diff) | |
| download | yosys-ffbd813a8c640f5653a0b8e9f54acbe398c2cf2e.tar.gz yosys-ffbd813a8c640f5653a0b8e9f54acbe398c2cf2e.tar.bz2 yosys-ffbd813a8c640f5653a0b8e9f54acbe398c2cf2e.zip | |
Merge pull request #2550 from zachjs/macro-arg-spaces
verilog: allow spaces in macro arguments
Diffstat (limited to 'tests/verilog/task_attr.ys')
0 files changed, 0 insertions, 0 deletions