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| author | Zachary Snow <zach@zachjs.com> | 2021-03-24 11:23:23 -0400 |
|---|---|---|
| committer | Zachary Snow <zachary.j.snow@gmail.com> | 2021-03-25 10:44:08 -0400 |
| commit | d6d5c2ef342240bd8adb925055667d140cb8dd29 (patch) | |
| tree | 069932d678d17ea40892c14786ef8faa1f15701c /tests/verilog/unbased_unsized.ys | |
| parent | 4762ed90ff6d3f1e9342fd306f97cae91960e2bd (diff) | |
| download | yosys-d6d5c2ef342240bd8adb925055667d140cb8dd29.tar.gz yosys-d6d5c2ef342240bd8adb925055667d140cb8dd29.tar.bz2 yosys-d6d5c2ef342240bd8adb925055667d140cb8dd29.zip | |
rtlil: add const accessors for modules, wires, and cells
Diffstat (limited to 'tests/verilog/unbased_unsized.ys')
0 files changed, 0 insertions, 0 deletions