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| author | Jannis Harder <me@jix.one> | 2023-04-24 16:08:48 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-04-24 16:08:48 +0200 |
| commit | cee3cb31b98e3b67af3165969c8cfc0616c37e19 (patch) | |
| tree | f146d725bdaf0262f04bcd6092a34abbd127f3ad /tests/verilog/unbased_unsized_shift.ys | |
| parent | 51dd0290241c521f5498f71f4fd4fb0598d83a76 (diff) | |
| parent | 985f4926b77aef98a2639624a44e155b2233c3ad (diff) | |
| download | yosys-cee3cb31b98e3b67af3165969c8cfc0616c37e19.tar.gz yosys-cee3cb31b98e3b67af3165969c8cfc0616c37e19.tar.bz2 yosys-cee3cb31b98e3b67af3165969c8cfc0616c37e19.zip | |
verilog: Fix const eval of unbased unsized constants
Diffstat (limited to 'tests/verilog/unbased_unsized_shift.ys')
| -rw-r--r-- | tests/verilog/unbased_unsized_shift.ys | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/tests/verilog/unbased_unsized_shift.ys b/tests/verilog/unbased_unsized_shift.ys new file mode 100644 index 000000000..c36049600 --- /dev/null +++ b/tests/verilog/unbased_unsized_shift.ys @@ -0,0 +1,7 @@ +read_verilog -sv unbased_unsized_shift.sv +hierarchy +proc +flatten +opt -full +select -module top +sat -verify -seq 1 -tempinduct -prove-asserts -show-all |