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| author | Zachary Snow <zach@zachjs.com> | 2021-01-20 09:15:48 -0700 |
|---|---|---|
| committer | Zachary Snow <zach@zachjs.com> | 2021-01-20 09:16:21 -0700 |
| commit | 006c18fc112a686a20b2b138ddc3bf773ee2f2f5 (patch) | |
| tree | 9f6fc3b77e4aa65f4184dacca4871bb318280827 /tests/verilog/wire_and_var.ys | |
| parent | 4762cc06c6b7cd36dda2e6eddf15b9782334ccd4 (diff) | |
| download | yosys-006c18fc112a686a20b2b138ddc3bf773ee2f2f5.tar.gz yosys-006c18fc112a686a20b2b138ddc3bf773ee2f2f5.tar.bz2 yosys-006c18fc112a686a20b2b138ddc3bf773ee2f2f5.zip | |
sv: fix support wire and var data type modifiers
Diffstat (limited to 'tests/verilog/wire_and_var.ys')
| -rw-r--r-- | tests/verilog/wire_and_var.ys | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/tests/verilog/wire_and_var.ys b/tests/verilog/wire_and_var.ys new file mode 100644 index 000000000..9359a9d55 --- /dev/null +++ b/tests/verilog/wire_and_var.ys @@ -0,0 +1,9 @@ +logger -expect warning "wire '\\wire_1' is assigned in a block" 1 +logger -expect warning "reg '\\reg_2' is assigned in a continuous assignment" 1 + +logger -expect warning "reg '\\var_reg_2' is assigned in a continuous assignment" 1 + +logger -expect warning "wire '\\wire_logic_1' is assigned in a block" 1 +logger -expect warning "wire '\\wire_integer_1' is assigned in a block" 1 + +read_verilog -sv wire_and_var.sv |