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| author | whitequark <whitequark@whitequark.org> | 2021-02-05 06:49:34 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-02-05 06:49:34 +0000 |
| commit | 3d9898272a5afd60f6080603bf065056d9dca000 (patch) | |
| tree | 600f7d8df8c2d9958053b56f60a3135c712c1e3d /tests/verilog | |
| parent | 7c6bf42db8cf8e269b04591a80d8e085e072059a (diff) | |
| parent | 98c4feb72ff52f12aadd34b0deccb819d701ff2c (diff) | |
| download | yosys-3d9898272a5afd60f6080603bf065056d9dca000.tar.gz yosys-3d9898272a5afd60f6080603bf065056d9dca000.tar.bz2 yosys-3d9898272a5afd60f6080603bf065056d9dca000.zip | |
Merge pull request #2572 from antmicro/check-labels
verilog_parser: add label check to gen_block
Diffstat (limited to 'tests/verilog')
| -rw-r--r-- | tests/verilog/block_labels.ys | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/tests/verilog/block_labels.ys b/tests/verilog/block_labels.ys new file mode 100644 index 000000000..e76bcf771 --- /dev/null +++ b/tests/verilog/block_labels.ys @@ -0,0 +1,26 @@ +read_verilog <<EOT +module foo; + + genvar a = 0; + for (a = 0; a < 10; a++) begin : a + end : a +endmodule +EOT +read_verilog <<EOT +module foo2; + + genvar a = 0; + for (a = 0; a < 10; a++) begin : a + end +endmodule +EOT + +logger -expect error "Begin label \(a\) and end label \(b\) don't match\." 1 +read_verilog <<EOT +module foo3; + + genvar a = 0; + for (a = 0; a < 10; a++) begin : a + end : b +endmodule +EOT |