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| author | SergeyDegtyar <sndegtyar@gmail.com> | 2019-09-11 17:01:19 +0300 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-17 17:10:02 +0200 |
| commit | 7bc8f0c2e234641b8af7f8dd991ea65bd9a6ef1a (patch) | |
| tree | 7972341001cc4577926ef0590278f024c35edbf9 /tests/xilinx/adffs.v | |
| parent | 489444bcba0d54a45605872eb466792f07357f84 (diff) | |
| download | yosys-7bc8f0c2e234641b8af7f8dd991ea65bd9a6ef1a.tar.gz yosys-7bc8f0c2e234641b8af7f8dd991ea65bd9a6ef1a.tar.bz2 yosys-7bc8f0c2e234641b8af7f8dd991ea65bd9a6ef1a.zip | |
Add comment with expected behavior for latches,tribuf tests;Update adffs test
Diffstat (limited to 'tests/xilinx/adffs.v')
| -rw-r--r-- | tests/xilinx/adffs.v | 18 |
1 files changed, 7 insertions, 11 deletions
diff --git a/tests/xilinx/adffs.v b/tests/xilinx/adffs.v index 93c8bf52c..05e68caf7 100644 --- a/tests/xilinx/adffs.v +++ b/tests/xilinx/adffs.v @@ -22,30 +22,26 @@ module adffn q <= d; endmodule -module dffsr +module dffs ( input d, clk, pre, clr, output reg q ); initial begin q = 0; end - always @( posedge clk, posedge pre, posedge clr ) - if ( clr ) - q <= 1'b0; - else if ( pre ) + always @( posedge clk ) + if ( pre ) q <= 1'b1; else q <= d; endmodule -module ndffnsnr +module ndffnr ( input d, clk, pre, clr, output reg q ); initial begin q = 0; end - always @( negedge clk, negedge pre, negedge clr ) + always @( negedge clk ) if ( !clr ) q <= 1'b0; - else if ( !pre ) - q <= 1'b1; else q <= d; endmodule @@ -58,7 +54,7 @@ input a, output b,b1,b2,b3 ); -dffsr u_dffsr ( +dffs u_dffs ( .clk (clk ), .clr (clr), .pre (pre), @@ -66,7 +62,7 @@ dffsr u_dffsr ( .q (b ) ); -ndffnsnr u_ndffnsnr ( +ndffnr u_ndffnr ( .clk (clk ), .clr (clr), .pre (pre), |