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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-27 12:50:20 -0700 |
|---|---|---|
| committer | Marcin KoĆcielnicki <koriakin@0x04.net> | 2019-09-30 12:52:43 +0200 |
| commit | 6216e45edae11fa3cc6e45a65762e5c215af0904 (patch) | |
| tree | efaa84b394220244d219a85b9cea35e7920bfa24 /tests/xilinx/latches.v | |
| parent | 5b5756b91ee6b514021afbe857135801f3cdcc33 (diff) | |
| download | yosys-6216e45edae11fa3cc6e45a65762e5c215af0904.tar.gz yosys-6216e45edae11fa3cc6e45a65762e5c215af0904.tar.bz2 yosys-6216e45edae11fa3cc6e45a65762e5c215af0904.zip | |
Add latch test modified from #1363
Diffstat (limited to 'tests/xilinx/latches.v')
| -rw-r--r-- | tests/xilinx/latches.v | 58 |
1 files changed, 58 insertions, 0 deletions
diff --git a/tests/xilinx/latches.v b/tests/xilinx/latches.v new file mode 100644 index 000000000..83bad7f35 --- /dev/null +++ b/tests/xilinx/latches.v @@ -0,0 +1,58 @@ +module latchp + ( input d, en, output reg q ); + always @* + if ( en ) + q <= d; +endmodule + +module latchn + ( input d, en, output reg q ); + always @* + if ( !en ) + q <= d; +endmodule + +module latchsr + ( input d, en, clr, pre, output reg q ); + always @* + if ( clr ) + q <= 1'b0; + else if ( pre ) + q <= 1'b1; + else if ( en ) + q <= d; +endmodule + + +module top ( +input clk, +input clr, +input pre, +input a, +output b,b1,b2 +); + + +latchp u_latchp ( + .en (clk ), + .d (a ), + .q (b ) + ); + + +latchn u_latchn ( + .en (clk ), + .d (a ), + .q (b1 ) + ); + + +latchsr u_latchsr ( + .en (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b2 ) + ); + +endmodule |
