diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-18 12:44:34 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-18 12:44:34 -0700 |
| commit | c663a3680b13422c568e3dc438e7b971b81a71c3 (patch) | |
| tree | 8ef67b81d26f7d46ef76fb46a3f36127ae34ddbf /tests/xilinx/mul_unsigned.ys | |
| parent | f7dbfef7926e7239d83c8e9734f3d14edea46f80 (diff) | |
| download | yosys-c663a3680b13422c568e3dc438e7b971b81a71c3.tar.gz yosys-c663a3680b13422c568e3dc438e7b971b81a71c3.tar.bz2 yosys-c663a3680b13422c568e3dc438e7b971b81a71c3.zip | |
Remove stat
Diffstat (limited to 'tests/xilinx/mul_unsigned.ys')
| -rw-r--r-- | tests/xilinx/mul_unsigned.ys | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/tests/xilinx/mul_unsigned.ys b/tests/xilinx/mul_unsigned.ys index 30c034afe..77990bd68 100644 --- a/tests/xilinx/mul_unsigned.ys +++ b/tests/xilinx/mul_unsigned.ys @@ -4,7 +4,6 @@ hierarchy -top mul_unsigned equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mul_unsigned # Constrain all select calls below inside the top module -stat select -assert-count 1 t:BUFG select -assert-count 1 t:DSP48E1 select -assert-count 30 t:FDRE |