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author | Eddie Hung <eddie@fpgeh.com> | 2019-11-19 15:40:39 -0800 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-19 15:40:39 -0800 |
commit | 09ee96e8c22ec692ee3ee31b8c211646eabbcf27 (patch) | |
tree | 8b24dad9db0013ee3db20326b00941bd2abb10d1 /tests/xilinx/xilinx_srl.v | |
parent | 304e5f9ea45b8a4e2a28aba7f2820d1862377fef (diff) | |
parent | 7ea0a5937ba2572f6d9d62e73e24df480c49561d (diff) | |
download | yosys-09ee96e8c22ec692ee3ee31b8c211646eabbcf27.tar.gz yosys-09ee96e8c22ec692ee3ee31b8c211646eabbcf27.tar.bz2 yosys-09ee96e8c22ec692ee3ee31b8c211646eabbcf27.zip |
Merge remote-tracking branch 'origin/master' into xaig_dff
Diffstat (limited to 'tests/xilinx/xilinx_srl.v')
-rw-r--r-- | tests/xilinx/xilinx_srl.v | 40 |
1 files changed, 0 insertions, 40 deletions
diff --git a/tests/xilinx/xilinx_srl.v b/tests/xilinx/xilinx_srl.v deleted file mode 100644 index bc2a15ab2..000000000 --- a/tests/xilinx/xilinx_srl.v +++ /dev/null @@ -1,40 +0,0 @@ -module xilinx_srl_static_test(input i, clk, output [1:0] q); -reg head = 1'b0; -reg [3:0] shift1 = 4'b0000; -reg [3:0] shift2 = 4'b0000; - -always @(posedge clk) begin - head <= i; - shift1 <= {shift1[2:0], head}; - shift2 <= {shift2[2:0], head}; -end - -assign q = {shift2[3], shift1[3]}; -endmodule - -module xilinx_srl_variable_test(input i, clk, input [1:0] l1, l2, output [1:0] q); -reg head = 1'b0; -reg [3:0] shift1 = 4'b0000; -reg [3:0] shift2 = 4'b0000; - -always @(posedge clk) begin - head <= i; - shift1 <= {shift1[2:0], head}; - shift2 <= {shift2[2:0], head}; -end - -assign q = {shift2[l2], shift1[l1]}; -endmodule - -module $__XILINX_SHREG_(input C, D, E, input [1:0] L, output Q); -parameter CLKPOL = 1; -parameter ENPOL = 1; -parameter DEPTH = 1; -parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}}; -reg [DEPTH-1:0] r = INIT; -wire clk = C ^ CLKPOL; -always @(posedge C) - if (E) - r <= { r[DEPTH-2:0], D }; -assign Q = r[L]; -endmodule |