diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-19 15:40:39 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-19 15:40:39 -0800 |
| commit | 09ee96e8c22ec692ee3ee31b8c211646eabbcf27 (patch) | |
| tree | 8b24dad9db0013ee3db20326b00941bd2abb10d1 /tests/xilinx/xilinx_srl.ys | |
| parent | 304e5f9ea45b8a4e2a28aba7f2820d1862377fef (diff) | |
| parent | 7ea0a5937ba2572f6d9d62e73e24df480c49561d (diff) | |
| download | yosys-09ee96e8c22ec692ee3ee31b8c211646eabbcf27.tar.gz yosys-09ee96e8c22ec692ee3ee31b8c211646eabbcf27.tar.bz2 yosys-09ee96e8c22ec692ee3ee31b8c211646eabbcf27.zip | |
Merge remote-tracking branch 'origin/master' into xaig_dff
Diffstat (limited to 'tests/xilinx/xilinx_srl.ys')
| -rw-r--r-- | tests/xilinx/xilinx_srl.ys | 67 |
1 files changed, 0 insertions, 67 deletions
diff --git a/tests/xilinx/xilinx_srl.ys b/tests/xilinx/xilinx_srl.ys deleted file mode 100644 index b8df0e55a..000000000 --- a/tests/xilinx/xilinx_srl.ys +++ /dev/null @@ -1,67 +0,0 @@ -read_verilog xilinx_srl.v -design -save read - -design -copy-to model $__XILINX_SHREG_ -hierarchy -top xilinx_srl_static_test -prep -design -save gold - -techmap -xilinx_srl -fixed -opt - -# stat -# show -width -select -assert-count 1 t:$_DFF_P_ -select -assert-count 2 t:$__XILINX_SHREG_ - -design -stash gate - -design -import gold -as gold -design -import gate -as gate -design -copy-from model -as $__XILINX_SHREG_ \$__XILINX_SHREG_ -prep - -miter -equiv -flatten -make_assert -make_outputs gold gate miter -dump gate -sat -verify -prove-asserts -show-ports -seq 5 miter - -#design -load gold -#stat - -#design -load gate -#stat - -########## - -design -load read -design -copy-to model $__XILINX_SHREG_ -hierarchy -top xilinx_srl_variable_test -prep -design -save gold - -xilinx_srl -variable -opt - -#stat -# show -width -# write_verilog -noexpr -norename -select -assert-count 1 t:$dff -select -assert-count 1 t:$dff r:WIDTH=1 %i -select -assert-count 2 t:$__XILINX_SHREG_ - -design -stash gate - -design -import gold -as gold -design -import gate -as gate -design -copy-from model -as $__XILINX_SHREG_ \$__XILINX_SHREG_ -prep - -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -show-ports -seq 5 miter - -# design -load gold -# stat - -# design -load gate -# stat |