diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-10-08 13:03:06 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-10-08 13:03:06 -0700 |
| commit | 304e5f9ea45b8a4e2a28aba7f2820d1862377fef (patch) | |
| tree | be1d59d00acdcab765a2f2d43117a640d79a6d03 /tests/xilinx | |
| parent | 4f0818275fe44c451be59235616061be8ff5e382 (diff) | |
| parent | 3fb604c75d3e8ee45d35fac8b787cb95a8adcf84 (diff) | |
| download | yosys-304e5f9ea45b8a4e2a28aba7f2820d1862377fef.tar.gz yosys-304e5f9ea45b8a4e2a28aba7f2820d1862377fef.tar.bz2 yosys-304e5f9ea45b8a4e2a28aba7f2820d1862377fef.zip | |
Merge remote-tracking branch 'origin/master' into xaig_dff
Diffstat (limited to 'tests/xilinx')
| -rw-r--r-- | tests/xilinx/latches.ys | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/tests/xilinx/latches.ys b/tests/xilinx/latches.ys index ac1102896..bd1dffd21 100644 --- a/tests/xilinx/latches.ys +++ b/tests/xilinx/latches.ys @@ -2,9 +2,7 @@ read_verilog latches.v proc flatten -equiv_opt -assert -run :prove -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -async2sync -equiv_opt -assert -run prove: -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load preopt synth_xilinx |