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| author | clairexen <claire@symbioticeda.com> | 2020-07-23 18:21:20 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-07-23 18:21:20 +0200 |
| commit | 02583ad50453ec332c4745d97eca67d720f1442e (patch) | |
| tree | ec9e4915826e3d3c58a38f539f9caf71f7ae98f9 /tests | |
| parent | 819f1d8c20e07da66122292b90603867b78ff2d2 (diff) | |
| parent | 4d9d90079c6e069fcba7ce04e8005285f4f237fe (diff) | |
| download | yosys-02583ad50453ec332c4745d97eca67d720f1442e.tar.gz yosys-02583ad50453ec332c4745d97eca67d720f1442e.tar.bz2 yosys-02583ad50453ec332c4745d97eca67d720f1442e.zip | |
Merge pull request #2294 from Ravenslofty/intel_alm_timings
intel_alm: add additional ABC9 timings
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/arch/intel_alm/mux.ys | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/tests/arch/intel_alm/mux.ys b/tests/arch/intel_alm/mux.ys index d109257bd..8277e925f 100644 --- a/tests/arch/intel_alm/mux.ys +++ b/tests/arch/intel_alm/mux.ys @@ -47,10 +47,9 @@ proc equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux8 # Constrain all select calls below inside the top module -select -assert-count 1 t:MISTRAL_ALUT3 -select -assert-count 1 t:MISTRAL_ALUT5 -select -assert-count 2 t:MISTRAL_ALUT6 -select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D +select -assert-count 3 t:MISTRAL_ALUT5 +select -assert-count 1 t:MISTRAL_ALUT6 +select -assert-none t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D design -load read @@ -70,10 +69,9 @@ proc equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module -select -assert-count 1 t:MISTRAL_ALUT3 select -assert-count 2 t:MISTRAL_ALUT5 select -assert-count 4 t:MISTRAL_ALUT6 -select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D +select -assert-none t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D design -load read |