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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-30 14:20:47 -0700 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-17 17:10:02 +0200 |
| commit | 08bd1816e39d2abfbe36ce0b58c0d4506db303e4 (patch) | |
| tree | 08c587f82a1565a4e04240ec0f0316687ad5f141 /tests | |
| parent | a12801843bb400bba8f2f8ce99a3f524ac05b7e8 (diff) | |
| download | yosys-08bd1816e39d2abfbe36ce0b58c0d4506db303e4.tar.gz yosys-08bd1816e39d2abfbe36ce0b58c0d4506db303e4.tar.bz2 yosys-08bd1816e39d2abfbe36ce0b58c0d4506db303e4.zip | |
Update area for div_mod
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/xilinx/div_mod.ys | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/tests/xilinx/div_mod.ys b/tests/xilinx/div_mod.ys index 4518db8bf..da7e60a9a 100644 --- a/tests/xilinx/div_mod.ys +++ b/tests/xilinx/div_mod.ys @@ -6,12 +6,12 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd top # Constrain all select calls below inside the top module select -assert-count 12 t:LUT1 -select -assert-count 23 t:LUT2 -select -assert-count 12 t:LUT4 -select -assert-count 9 t:LUT5 -select -assert-count 84 t:LUT6 +select -assert-count 19 t:LUT2 +select -assert-count 13 t:LUT4 +select -assert-count 6 t:LUT5 +select -assert-count 82 t:LUT6 select -assert-count 65 t:MUXCY -select -assert-count 39 t:MUXF7 -select -assert-count 15 t:MUXF8 +select -assert-count 37 t:MUXF7 +select -assert-count 11 t:MUXF8 select -assert-count 28 t:XORCY select -assert-none t:LUT1 t:LUT2 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D |