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authorEddie Hung <eddie@fpgeh.com>2019-05-03 15:35:26 -0700
committerEddie Hung <eddie@fpgeh.com>2019-05-03 15:35:26 -0700
commit09841c2ac1f36d06faada27093a2cf0cdfb6cb42 (patch)
treed32f3475fba92e1f529e1117680c651aff0eba36 /tests
parentd9c4644e88b916d1eadfd401abf297c0995b6462 (diff)
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Add quick-and-dirty specify tests
Diffstat (limited to 'tests')
-rw-r--r--tests/various/specify.v28
-rw-r--r--tests/various/specify.ys25
2 files changed, 53 insertions, 0 deletions
diff --git a/tests/various/specify.v b/tests/various/specify.v
new file mode 100644
index 000000000..aea0d0fc5
--- /dev/null
+++ b/tests/various/specify.v
@@ -0,0 +1,28 @@
+module test (
+ input EN, CLK,
+ input [3:0] D,
+ output reg [3:0] Q
+);
+ always @(posedge CLK)
+ if (EN) Q <= D;
+
+ specify
+ if (EN) (CLK *> (Q : D)) = (1, 2:3:4);
+ $setup(D, posedge CLK &&& EN, 5);
+ $hold(posedge CLK, D &&& EN, 6);
+ endspecify
+endmodule
+
+module test2 (
+ input A, B,
+ output Q
+);
+ xor (Q, A, B);
+ specify
+ //specparam T_rise = 1;
+ //specparam T_fall = 2;
+ `define T_rise 1
+ `define T_fall 2
+ (A => Q) = (`T_rise,`T_fall);
+ endspecify
+endmodule
diff --git a/tests/various/specify.ys b/tests/various/specify.ys
new file mode 100644
index 000000000..c4e901705
--- /dev/null
+++ b/tests/various/specify.ys
@@ -0,0 +1,25 @@
+read_verilog -specify specify.v
+prep
+cd test
+select t:$specify2 -assert-count 0
+select t:$specify3 -assert-count 1
+select t:$specrule -assert-count 2
+cd test2
+select t:$specify2 -assert-count 1
+select t:$specify3 -assert-count 0
+select t:$specrule -assert-count 0
+write_verilog specify.out
+design -stash gold
+
+read_verilog -specify specify.out
+cd test
+select t:$specify2 -assert-count 0
+select t:$specify3 -assert-count 1
+select t:$specrule -assert-count 2
+cd test2
+select t:$specify2 -assert-count 1
+select t:$specify3 -assert-count 0
+select t:$specrule -assert-count 0
+design -stash gate
+
+# TODO: How to check $specify and $specrule-s are equivalent?