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| author | Pepijn de Vos <pepijndevos@gmail.com> | 2019-11-06 19:48:18 +0100 |
|---|---|---|
| committer | Pepijn de Vos <pepijndevos@gmail.com> | 2019-11-06 19:48:18 +0100 |
| commit | 0e5dbc4abc2fb3a0d98d2dfb07e8642058d69bb1 (patch) | |
| tree | 551985ca52e16aa63ebd869df7ed6dec0d78717f /tests | |
| parent | df8390f5df9868b583ce88a4d2ce41511fab2f7b (diff) | |
| download | yosys-0e5dbc4abc2fb3a0d98d2dfb07e8642058d69bb1.tar.gz yosys-0e5dbc4abc2fb3a0d98d2dfb07e8642058d69bb1.tar.bz2 yosys-0e5dbc4abc2fb3a0d98d2dfb07e8642058d69bb1.zip | |
fix wide luts
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/arch/gowin/mux.ys | 17 |
1 files changed, 10 insertions, 7 deletions
diff --git a/tests/arch/gowin/mux.ys b/tests/arch/gowin/mux.ys index f7e478c87..4990be421 100644 --- a/tests/arch/gowin/mux.ys +++ b/tests/arch/gowin/mux.ys @@ -15,33 +15,36 @@ select -assert-none t:LUT3 t:IBUF t:OBUF %% t:* %D design -load read hierarchy -top mux4 proc -equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin -nowidelut # equivalency check +equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux4 # Constrain all select calls below inside the top module -select -assert-count 2 t:LUT4 +select -assert-count 4 t:LUT4 +select -assert-count 2 t:MUX2_LUT5 +select -assert-count 1 t:MUX2_LUT6 select -assert-count 6 t:IBUF select -assert-count 1 t:OBUF -select -assert-none t:LUT4 t:IBUF t:OBUF %% t:* %D +select -assert-none t:LUT4 t:MUX2_LUT6 t:MUX2_LUT5 t:IBUF t:OBUF %% t:* %D design -load read hierarchy -top mux8 proc -equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin -nowidelut # equivalency check +equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux8 # Constrain all select calls below inside the top module select -assert-count 11 t:IBUF select -assert-count 1 t:OBUF -select -assert-none t:LUT4 t:IBUF t:OBUF %% t:* %D +select -assert-none t:LUT4 t:MUX2_LUT6 t:MUX2_LUT5 t:IBUF t:OBUF %% t:* %D design -load read hierarchy -top mux16 proc -equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin -nowidelut # equivalency check +equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module select -assert-count 20 t:IBUF select -assert-count 1 t:OBUF +show -select -assert-none t:LUT4 t:LUT3 t:IBUF t:OBUF %% t:* %D +select -assert-none t:LUT4 t:MUX2_LUT6 t:MUX2_LUT5 t:MUX2_LUT6 t:MUX2_LUT7 t:MUX2_LUT8 t:IBUF t:OBUF %% t:* %D |