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| author | SergeyDegtyar <sndegtyar@gmail.com> | 2019-08-30 15:22:46 +0300 |
|---|---|---|
| committer | SergeyDegtyar <sndegtyar@gmail.com> | 2019-08-30 15:22:46 +0300 |
| commit | 17c92dc679458a9ffabd76e2ce8e2491bd249110 (patch) | |
| tree | 4ffdbeaa97fada307badb76bac396e5638077e97 /tests | |
| parent | 94a56c14b78a2872d65bb30371151e934a259275 (diff) | |
| download | yosys-17c92dc679458a9ffabd76e2ce8e2491bd249110.tar.gz yosys-17c92dc679458a9ffabd76e2ce8e2491bd249110.tar.bz2 yosys-17c92dc679458a9ffabd76e2ce8e2491bd249110.zip | |
Fix macc test
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/ice40/macc.ys | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/ice40/macc.ys b/tests/ice40/macc.ys index 233e7e890..d65c31b73 100644 --- a/tests/ice40/macc.ys +++ b/tests/ice40/macc.ys @@ -4,7 +4,7 @@ hierarchy -top top equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 41 t:SB_LUT4 +select -assert-count 38 t:SB_LUT4 select -assert-count 6 t:SB_CARRY select -assert-count 7 t:SB_DFFSR select -assert-none t:SB_LUT4 t:SB_CARRY t:SB_DFFSR %% t:* %D |