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| author | Eddie Hung <eddie@fpgeh.com> | 2020-02-19 10:45:10 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-02-19 10:45:10 -0800 |
| commit | 1d401a7991f4c0f133b7355acc400132da1aa4a0 (patch) | |
| tree | 2064e3fcb06fcab66bf4d3d968ea050e8773b702 /tests | |
| parent | d20c1dac73e344dda73ec2b526ffb764efc9fdd8 (diff) | |
| download | yosys-1d401a7991f4c0f133b7355acc400132da1aa4a0.tar.gz yosys-1d401a7991f4c0f133b7355acc400132da1aa4a0.tar.bz2 yosys-1d401a7991f4c0f133b7355acc400132da1aa4a0.zip | |
clean: ignore specify-s inside cells when determining whether to keep
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/various/specify.ys | 21 |
1 files changed, 20 insertions, 1 deletions
diff --git a/tests/various/specify.ys b/tests/various/specify.ys index a2b6038e4..9d55b8eb5 100644 --- a/tests/various/specify.ys +++ b/tests/various/specify.ys @@ -55,4 +55,23 @@ equiv_induct -seq 5 equiv_status -assert design -reset -read_verilog specify.v +read_verilog -specify <<EOT +(* blackbox *) +module test7_sub(input i, output o); +specify + (i => o) = 1; +endspecify +assign o = ~i; +endmodule + +module test7(input i, output o); + wire w; + test7_sub unused(i, w); + test7_sub used(i, o); +endmodule +EOT +hierarchy +cd test7 +clean +select -assert-count 1 c:used +select -assert-none c:* c:used %d |