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| author | Miodrag Milanović <mmicko@gmail.com> | 2022-01-19 08:49:58 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-01-19 08:49:58 +0100 |
| commit | 4525e419f64da95e37eba7c8b43972ab7349800d (patch) | |
| tree | c97ad2f4dcbc324b8d548382ef63bcc67b3308ac /tests | |
| parent | 59382945a9169b01a8b1b30b5e988e56e4912f06 (diff) | |
| parent | c2b7ad3b28ebd7865c8b2e795b2942d5d1bd00f5 (diff) | |
| download | yosys-4525e419f64da95e37eba7c8b43972ab7349800d.tar.gz yosys-4525e419f64da95e37eba7c8b43972ab7349800d.tar.bz2 yosys-4525e419f64da95e37eba7c8b43972ab7349800d.zip | |
Merge pull request #3120 from Icenowy/anlogic-bram
anlogic: support BRAM mapping
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/arch/anlogic/blockram.ys | 13 | ||||
| -rw-r--r-- | tests/arch/anlogic/lutram.ys | 2 |
2 files changed, 14 insertions, 1 deletions
diff --git a/tests/arch/anlogic/blockram.ys b/tests/arch/anlogic/blockram.ys new file mode 100644 index 000000000..da23409ba --- /dev/null +++ b/tests/arch/anlogic/blockram.ys @@ -0,0 +1,13 @@ +read_verilog ../common/blockram.v +hierarchy -top sync_ram_sp +proc +memory -nomap +equiv_opt -run :prove -map +/anlogic/cells_sim.v synth_anlogic +memory +opt -full + +design -load postopt +cd sync_ram_sp + +select -assert-count 1 t:EG_PHY_BRAM +select -assert-none t:EG_PHY_BRAM %% t:* %D diff --git a/tests/arch/anlogic/lutram.ys b/tests/arch/anlogic/lutram.ys index 6dbdbdac3..fe6135c73 100644 --- a/tests/arch/anlogic/lutram.ys +++ b/tests/arch/anlogic/lutram.ys @@ -2,7 +2,7 @@ read_verilog ../common/lutram.v hierarchy -top lutram_1w1r proc memory -nomap -equiv_opt -run :prove -map +/anlogic/cells_sim.v synth_anlogic +equiv_opt -run :prove -map +/anlogic/cells_sim.v synth_anlogic -nobram memory opt -full |