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| author | Eddie Hung <eddie@fpgeh.com> | 2020-04-16 10:24:02 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-14 10:33:56 -0700 |
| commit | 48052ad813db3561a959a1921466d571bafa354c (patch) | |
| tree | 9029ab8f94665a252449cfa4f0a0440ed0696815 /tests | |
| parent | 7812a2959b9b23b44e8144f9edb139f282d623e1 (diff) | |
| download | yosys-48052ad813db3561a959a1921466d571bafa354c.tar.gz yosys-48052ad813db3561a959a1921466d571bafa354c.tar.bz2 yosys-48052ad813db3561a959a1921466d571bafa354c.zip | |
abc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ too
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/various/abc9.ys | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/tests/various/abc9.ys b/tests/various/abc9.ys index 6e2415ad7..7a3a503e4 100644 --- a/tests/various/abc9.ys +++ b/tests/various/abc9.ys @@ -45,14 +45,16 @@ sat -seq 10 -verify -prove-asserts -show-ports miter design -reset read_verilog -icells <<EOT module abc9_test036(input clk, d, output q); -(* keep *) reg w; -$__ABC9_FF_ ff(.D(d), .Q(w)); -wire \ff.clock = clk; -wire \ff.init = 1'b0; +(* keep, init=1'b0 *) wire w; +$_DFF_P_ ff(.C(clk), .D(d), .Q(w)); assign q = w; endmodule EOT -abc9 -lut 4 -dff +equiv_opt abc9 -lut 4 -dff +design -load postopt +cd abc9_test036 +select -assert-count 1 t:$_DFF_P_ +select -assert-none t:* t:$_DFF_P_ %d design -reset |