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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-15 14:36:05 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-15 14:36:05 -0800 |
| commit | 5918ede9bd7568d5a5156f20fdc4ce215d4968f8 (patch) | |
| tree | 69ece578fd875dc05381f3f71946c6a79edeb25f /tests | |
| parent | 05c8858a907f0f188f1687ede260c2e1a97efe38 (diff) | |
| download | yosys-5918ede9bd7568d5a5156f20fdc4ce215d4968f8.tar.gz yosys-5918ede9bd7568d5a5156f20fdc4ce215d4968f8.tar.bz2 yosys-5918ede9bd7568d5a5156f20fdc4ce215d4968f8.zip | |
abc9: aAdd test to check $_NOT_s are absorbed
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/techmap/abc9.ys | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/tests/techmap/abc9.ys b/tests/techmap/abc9.ys index 20f263da8..62b5dfef6 100644 --- a/tests/techmap/abc9.ys +++ b/tests/techmap/abc9.ys @@ -38,3 +38,15 @@ abc9 -lut 4 design -load gold scratchpad -copy abc9.script.flow3 abc9.script abc9 -lut 4 + + +design -reset +read_verilog -icells <<EOT +module top(input a, b, output o); +assign o = ~(a & b); +endmodule +EOT +abc9 -lut 4 +clean +select -assert-count 1 t:$lut +select -assert-none t:$lut t:* %D |