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| author | Clifford Wolf <clifford@clifford.at> | 2019-04-22 08:38:52 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-04-22 08:38:52 +0200 |
| commit | 632a6664484aefa6f9af1ace87ecefccd86d1957 (patch) | |
| tree | 4ed5fa744185b1a985f74e03cd2a1e5e4cb48d9c /tests | |
| parent | f84a84e3f1a27b361c21fcd30fcf50c1a6586629 (diff) | |
| parent | 7b35d5759289f7a3139c6eaa525ef737b8d5d82b (diff) | |
| download | yosys-632a6664484aefa6f9af1ace87ecefccd86d1957.tar.gz yosys-632a6664484aefa6f9af1ace87ecefccd86d1957.tar.bz2 yosys-632a6664484aefa6f9af1ace87ecefccd86d1957.zip | |
Merge pull request #945 from YosysHQ/clifford/libwb
New behavior for read_verilog handling of whiteboxes
Diffstat (limited to 'tests')
| -rwxr-xr-x | tests/tools/autotest.sh | 4 | ||||
| -rw-r--r-- | tests/various/hierarchy.sh | 1 |
2 files changed, 3 insertions, 2 deletions
diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh index f3dac504e..bb9c3bfb5 100755 --- a/tests/tools/autotest.sh +++ b/tests/tools/autotest.sh @@ -7,7 +7,7 @@ use_modelsim=false verbose=false keeprunning=false makejmode=false -frontend="verilog" +frontend="verilog -noblackbox" backend_opts="-noattr -noexpr -siminit" autotb_opts="" include_opts="" @@ -137,7 +137,7 @@ do egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.${ext} else "$toolsdir"/../../yosys -f "$frontend $include_opts" -b "verilog" -o ${bn}_ref.v ../${fn} - frontend="verilog" + frontend="verilog -noblackbox" fi if [ ! -f ../${bn}_tb.v ]; then diff --git a/tests/various/hierarchy.sh b/tests/various/hierarchy.sh index d33a247be..9dbd1c89f 100644 --- a/tests/various/hierarchy.sh +++ b/tests/various/hierarchy.sh @@ -53,6 +53,7 @@ echo -n " no explicit top - " module noTop(a, y); input a; output [31:0] y; + assign y = a; endmodule EOV hierarchy -auto-top |