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| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-27 01:02:16 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-27 01:02:16 -0800 |
| commit | 6338615aa173bebc9a971d7cb0fcad1220771bb2 (patch) | |
| tree | 201be44eac7febf25413c342566806337578ff7f /tests | |
| parent | f1538c3642176cb44a8b68349d69c4016f02ca81 (diff) | |
| parent | c7aa2c6b79243201d076b6e71a461865610c9e8b (diff) | |
| download | yosys-6338615aa173bebc9a971d7cb0fcad1220771bb2.tar.gz yosys-6338615aa173bebc9a971d7cb0fcad1220771bb2.tar.bz2 yosys-6338615aa173bebc9a971d7cb0fcad1220771bb2.zip | |
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/various/submod.ys | 25 |
1 files changed, 23 insertions, 2 deletions
diff --git a/tests/various/submod.ys b/tests/various/submod.ys index 7c6f555ac..552fd4e01 100644 --- a/tests/various/submod.ys +++ b/tests/various/submod.ys @@ -1,8 +1,8 @@ read_verilog <<EOT -module top(input a, output [1:0] b); +module top(input a, output b); wire c; (* submod="bar" *) sub s1(a, c); -assign b[0] = c; +assign b = c; endmodule module sub(input a, output c); @@ -48,3 +48,24 @@ design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter + + +design -reset +read_verilog -icells <<EOT +module top(input d, c, (* init = 3'b011 *) output reg [2:0] q); +(* submod="bar" *) DFF s1(.D(d), .C(c), .Q(q[1])); +DFF s2(.D(d), .C(c), .Q(q[0])); +DFF s3(.D(d), .C(c), .Q(q[2])); +endmodule + +module DFF(input D, C, output Q); +parameter INIT = 1'b0; +endmodule +EOT + +hierarchy -top top +proc + +submod +dffinit -ff DFF Q INIT +check -noinit -assert |