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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2020-07-24 13:08:54 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-07-31 00:08:15 +0200 |
| commit | 6cd135a5eb918d30aeaf295e3e9fab9bf73134fb (patch) | |
| tree | 9eed0a33bb64c46bd3cf0e65fd15c86344dd3e9f /tests | |
| parent | cf606998847a286a52f01d748372df396b59dd2b (diff) | |
| download | yosys-6cd135a5eb918d30aeaf295e3e9fab9bf73134fb.tar.gz yosys-6cd135a5eb918d30aeaf295e3e9fab9bf73134fb.tar.bz2 yosys-6cd135a5eb918d30aeaf295e3e9fab9bf73134fb.zip | |
opt_expr: Remove -clkinv option, make it the default.
Adds -noclkinv option just in case the old behavior was actually useful
to someone.
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/arch/xilinx/latches.ys | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/tests/arch/xilinx/latches.ys b/tests/arch/xilinx/latches.ys index e226c2ec8..ee87fee21 100644 --- a/tests/arch/xilinx/latches.ys +++ b/tests/arch/xilinx/latches.ys @@ -18,9 +18,8 @@ equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd latchn # Constrain all select calls below inside the top module select -assert-count 1 t:LDCE -select -assert-count 1 t:INV -select -assert-none t:LDCE t:INV %% t:* %D +select -assert-none t:LDCE %% t:* %D design -load read |