Merge pull request #1703 from YosysHQ/eddie/specify_improve

Improve specify parser

2 files changed, 47 insertions, 3 deletions

diff --git a/tests/various/specify.v b/tests/various/specify.v
index 5d44d78f7..c160d2ec4 100644
--- a/tests/various/specify.v
+++ b/tests/various/specify.v
@@ -7,11 +7,9 @@ module test (
 		if (EN) Q <= D;
 
 	specify
-`ifndef SKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS
 		if (EN) (posedge CLK *> (Q : D)) = (1, 2:3:4);
 		$setup(D, posedge CLK &&& EN, 5);
 		$hold(posedge CLK, D &&& EN, 6);
-`endif
 	endspecify
 endmodule
 
@@ -37,3 +35,30 @@ specify
   (posedge clk *> (q +: d)) = (3,1);
 endspecify
 endmodule
+
+module test3(input clk, input [1:0] d, output [1:0] q);
+specify
+  (posedge clk => (q +: d)) = (3,1);
+  (posedge clk *> (q +: d)) = (3,1);
+endspecify
+endmodule
+
+module test4(input clk, d, output q);
+specify
+  $setup(d, posedge clk, 1:2:3);
+  $setuphold(d, posedge clk, 1:2:3, 4:5:6);
+endspecify
+endmodule
+
+module test5(input clk, d, e, output q);
+specify
+  $setup(d, posedge clk &&& e, 1:2:3);
+endspecify
+endmodule
+
+module test6(input clk, d, e, output q);
+specify
+  (d[0] *> q[0]) = (3,1);
+  (posedge clk[0] => (q[0] +: d[0])) = (3,1);
+endspecify
+endmodule
diff --git a/tests/various/specify.ys b/tests/various/specify.ys
index 00597e1e2..9d55b8eb5 100644
--- a/tests/various/specify.ys
+++ b/tests/various/specify.ys
@@ -55,4 +55,23 @@ equiv_induct -seq 5
 equiv_status -assert
 design -reset
 
-read_verilog -DSKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS specify.v
+read_verilog -specify <<EOT
+(* blackbox *)
+module test7_sub(input i, output o);
+specify
+    (i => o) = 1;
+endspecify
+assign o = ~i;
+endmodule
+
+module test7(input i, output o);
+    wire w;
+    test7_sub unused(i, w);
+    test7_sub used(i, o);
+endmodule
+EOT
+hierarchy
+cd test7
+clean
+select -assert-count 1 c:used
+select -assert-none c:* c:used %d