diff options
| author | Marcelina Kościelnicka <mwk@0x04.net> | 2022-05-06 23:29:16 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2022-05-07 23:13:16 +0200 |
| commit | 77b1dfd8c3441d7552491c8e12eebcf4b369b52d (patch) | |
| tree | 3ee0d6d99fe6a7fd862f5067d26dedccd9602dc6 /tests | |
| parent | 048170d37681c274a8d7e0b36fa313c87d4e7ce9 (diff) | |
| download | yosys-77b1dfd8c3441d7552491c8e12eebcf4b369b52d.tar.gz yosys-77b1dfd8c3441d7552491c8e12eebcf4b369b52d.tar.bz2 yosys-77b1dfd8c3441d7552491c8e12eebcf4b369b52d.zip | |
opt_mem: Remove constant-value bit lanes.
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/techmap/.gitignore | 1 | ||||
| -rw-r--r-- | tests/techmap/mem_simple_4x1_runtest.sh | 16 |
2 files changed, 2 insertions, 15 deletions
diff --git a/tests/techmap/.gitignore b/tests/techmap/.gitignore index cfed22fc5..56c9ba8f9 100644 --- a/tests/techmap/.gitignore +++ b/tests/techmap/.gitignore @@ -1,2 +1,3 @@ *.log +*.out /*.mk diff --git a/tests/techmap/mem_simple_4x1_runtest.sh b/tests/techmap/mem_simple_4x1_runtest.sh index b486de5c7..5b5838b9d 100644 --- a/tests/techmap/mem_simple_4x1_runtest.sh +++ b/tests/techmap/mem_simple_4x1_runtest.sh @@ -1,17 +1,3 @@ #!/bin/bash -set -e - -../../yosys -b 'verilog -noattr' -o mem_simple_4x1_synth.v -p 'read_verilog mem_simple_4x1_uut.v; proc; opt; memory -nomap; techmap -map mem_simple_4x1_map.v;; techmap; opt; abc;; stat' - -iverilog -o mem_simple_4x1_gold_tb mem_simple_4x1_tb.v mem_simple_4x1_uut.v -iverilog -o mem_simple_4x1_gate_tb mem_simple_4x1_tb.v mem_simple_4x1_synth.v mem_simple_4x1_cells.v - -./mem_simple_4x1_gold_tb > mem_simple_4x1_gold_tb.out -./mem_simple_4x1_gate_tb > mem_simple_4x1_gate_tb.out - -diff -u mem_simple_4x1_gold_tb.out mem_simple_4x1_gate_tb.out -rm -f mem_simple_4x1_synth.v mem_simple_4x1_tb.vcd -rm -f mem_simple_4x1_{gold,gate}_tb{,.out} -: OK - +exec ../tools/autotest.sh -G -j $@ -p 'proc; opt; memory -nomap; techmap -map ../mem_simple_4x1_map.v;; techmap; opt; abc;; stat' mem_simple_4x1_uut.v |