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| author | Rodrigo Alejandro Melo <rodrigomelo9@gmail.com> | 2020-01-31 18:20:22 -0300 |
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| committer | Rodrigo Alejandro Melo <rodrigomelo9@gmail.com> | 2020-01-31 18:20:22 -0300 |
| commit | 7b3fe404ab30767a8b65f61fa2a6eebbe9019641 (patch) | |
| tree | 5498675a1b64bfe88e7c5a06e9d52b8a54eff31f /tests | |
| parent | a1c840ca5d6e8b580e21ae48550570aa9665741a (diff) | |
| download | yosys-7b3fe404ab30767a8b65f61fa2a6eebbe9019641.tar.gz yosys-7b3fe404ab30767a8b65f61fa2a6eebbe9019641.tar.bz2 yosys-7b3fe404ab30767a8b65f61fa2a6eebbe9019641.zip | |
$readmem[hb] file inclusion is now relative to the Verilog file
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
Diffstat (limited to 'tests')
0 files changed, 0 insertions, 0 deletions