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| author | SergeyDegtyar <sndegtyar@gmail.com> | 2019-09-04 14:57:45 +0300 |
|---|---|---|
| committer | SergeyDegtyar <sndegtyar@gmail.com> | 2019-09-04 14:57:45 +0300 |
| commit | 93f305b1c53ce49338bf276a7fb9c3aa4d578c9e (patch) | |
| tree | 759af959b7cc1a212ddd6610352f194c1ca04616 /tests | |
| parent | a203c8569cb6fc7093a5d09e4c64d8e545f81e39 (diff) | |
| download | yosys-93f305b1c53ce49338bf276a7fb9c3aa4d578c9e.tar.gz yosys-93f305b1c53ce49338bf276a7fb9c3aa4d578c9e.tar.bz2 yosys-93f305b1c53ce49338bf276a7fb9c3aa4d578c9e.zip | |
Remove stat command form shifter.ys test
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/ecp5/shifter.ys | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/ecp5/shifter.ys b/tests/ecp5/shifter.ys index 70fe6c45c..e1901e1a8 100644 --- a/tests/ecp5/shifter.ys +++ b/tests/ecp5/shifter.ys @@ -5,6 +5,6 @@ flatten equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -stat + select -assert-count 8 t:TRELLIS_FF select -assert-none t:TRELLIS_FF %% t:* %D |