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author | Eddie Hung <eddie@fpgeh.com> | 2019-09-19 15:47:41 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-19 15:47:41 -0700 |
commit | b88f0f6450a4d9db4c926a4636968f12d763096b (patch) | |
tree | 7c70b8294cc435e40d947ccbb44d7a6c1d7bc4de /tests | |
parent | 2d9484c12cd1fd96eca5253c876ad545ed209f40 (diff) | |
parent | b76fac3ac3a815568827a03b201f386b2577e010 (diff) | |
download | yosys-b88f0f6450a4d9db4c926a4636968f12d763096b.tar.gz yosys-b88f0f6450a4d9db4c926a4636968f12d763096b.tar.bz2 yosys-b88f0f6450a4d9db4c926a4636968f12d763096b.zip |
Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dsp
Diffstat (limited to 'tests')
-rw-r--r-- | tests/techmap/extractinv.ys | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/tests/techmap/extractinv.ys b/tests/techmap/extractinv.ys new file mode 100644 index 000000000..6146f829a --- /dev/null +++ b/tests/techmap/extractinv.ys @@ -0,0 +1,41 @@ +read_verilog << EOT + +module ff4(...); +parameter [0:0] CLK_INV = 1'b0; +parameter [3:0] DATA_INV = 4'b0000; +(* invertible_pin = "CLK_INV" *) +input clk; +(* invertible_pin = "DATA_INV" *) +input [3:0] d; +output [3:0] q; +endmodule + +module inv(...); +output o; +input i; +endmodule + +module top(...); +input d0, d1, d2, d3; +input clk; +output q; +ff4 #(.DATA_INV(4'h5)) ff_inst (.clk(clk), .d({d3, d2, d1, d0}), .q(q)); +endmodule + +EOT + +extractinv -inv inv o:i +clean + +select -assert-count 2 top/t:inv +select -assert-count 2 top/t:inv top/t:ff4 %ci:+[d] %ci:+[o] %i + +select -assert-count 1 top/t:inv top/w:d0 %co:+[i] %i +select -assert-count 0 top/t:inv top/w:d1 %co:+[i] %i +select -assert-count 1 top/t:inv top/w:d2 %co:+[i] %i +select -assert-count 0 top/t:inv top/w:d3 %co:+[i] %i + +select -assert-count 0 top/t:ff4 top/w:d0 %co:+[d] %i +select -assert-count 1 top/t:ff4 top/w:d1 %co:+[d] %i +select -assert-count 0 top/t:ff4 top/w:d2 %co:+[d] %i +select -assert-count 1 top/t:ff4 top/w:d3 %co:+[d] %i |