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| author | whitequark <whitequark@whitequark.org> | 2020-07-09 20:17:19 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-07-09 20:17:19 +0000 |
| commit | c0bcbe1f6254f050207a91506a63aa9d784bd8d6 (patch) | |
| tree | a788116d9cbdfe717123327895ea8a565a12ee39 /tests | |
| parent | 0e9b889b77454ce8bcee47e73ed9b79f9b31771f (diff) | |
| parent | dc35ef05f93bf634e7f158869af48707233505e2 (diff) | |
| download | yosys-c0bcbe1f6254f050207a91506a63aa9d784bd8d6.tar.gz yosys-c0bcbe1f6254f050207a91506a63aa9d784bd8d6.tar.bz2 yosys-c0bcbe1f6254f050207a91506a63aa9d784bd8d6.zip | |
Merge pull request #2255 from whitequark/bison-Werror-conflicts
verilog_parser: turn S/R and R/R conflicts into hard errors
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/various/integer_range_bad_syntax.ys | 6 | ||||
| -rw-r--r-- | tests/various/integer_real_bad_syntax.ys | 6 | ||||
| -rw-r--r-- | tests/various/logic_param_simple.ys | 9 | ||||
| -rw-r--r-- | tests/various/signed.ys | 28 |
4 files changed, 0 insertions, 49 deletions
diff --git a/tests/various/integer_range_bad_syntax.ys b/tests/various/integer_range_bad_syntax.ys deleted file mode 100644 index 4f427211f..000000000 --- a/tests/various/integer_range_bad_syntax.ys +++ /dev/null @@ -1,6 +0,0 @@ -logger -expect error "syntax error, unexpected" 1 -read_verilog -sv <<EOT -module test_integer_range(); -parameter integer [31:0] a = 0; -endmodule -EOT diff --git a/tests/various/integer_real_bad_syntax.ys b/tests/various/integer_real_bad_syntax.ys deleted file mode 100644 index 942d8de77..000000000 --- a/tests/various/integer_real_bad_syntax.ys +++ /dev/null @@ -1,6 +0,0 @@ -logger -expect error "syntax error, unexpected TOK_REAL" 1 -read_verilog -sv <<EOT -module test_integer_real(); -parameter integer real a = 0; -endmodule -EOT diff --git a/tests/various/logic_param_simple.ys b/tests/various/logic_param_simple.ys deleted file mode 100644 index 968564080..000000000 --- a/tests/various/logic_param_simple.ys +++ /dev/null @@ -1,9 +0,0 @@ -read_verilog -sv <<EOT -module test_logic_param(); -parameter logic a = 0; -parameter logic [31:0] e = 0; -parameter logic signed b = 0; -parameter logic unsigned c = 0; -parameter logic unsigned [31:0] d = 0; -endmodule -EOT diff --git a/tests/various/signed.ys b/tests/various/signed.ys deleted file mode 100644 index 2319a5da1..000000000 --- a/tests/various/signed.ys +++ /dev/null @@ -1,28 +0,0 @@ -# SV LRM A2.2.1 - -read_verilog -sv <<EOT -module test_signed(); -parameter integer signed a = 0; -parameter integer unsigned b = 0; - -endmodule -EOT - -design -reset -read_verilog -sv <<EOT -module test_signed(); -parameter logic signed [7:0] a = 0; -parameter logic unsigned [7:0] b = 0; - -endmodule -EOT - -design -reset -logger -expect error "syntax error, unexpected TOK_INTEGER" 1 -read_verilog -sv <<EOT -module test_signed(); -parameter signed integer a = 0; -parameter unsigned integer b = 0; - -endmodule -EOT |