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| author | Jannis Harder <me@jix.one> | 2022-04-01 21:03:20 +0200 |
|---|---|---|
| committer | Jannis Harder <me@jix.one> | 2022-04-01 21:03:20 +0200 |
| commit | ca5b910296c05c95f3bc7f2d1d2b7db19d6328e2 (patch) | |
| tree | 9cf51a65ac4706c2ece7d86a290aea4946b8bbde /tests | |
| parent | 2ec4af56e6ec83fe320cd7af958020ea56e1d9ab (diff) | |
| download | yosys-ca5b910296c05c95f3bc7f2d1d2b7db19d6328e2.tar.gz yosys-ca5b910296c05c95f3bc7f2d1d2b7db19d6328e2.tar.bz2 yosys-ca5b910296c05c95f3bc7f2d1d2b7db19d6328e2.zip | |
opt_merge: Add `-keepdc` option required for formal verification
The `-keepdc` option prevents merging flipflops with dont-care bits in
their initial value, as, in general, this is not a valid transform for
formal verification.
The keepdc option of `opt` is passed along to `opt_merge` now.
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/opt/opt_merge_init.ys | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/tests/opt/opt_merge_init.ys b/tests/opt/opt_merge_init.ys index 20b6cabee..7ee7d3dd7 100644 --- a/tests/opt/opt_merge_init.ys +++ b/tests/opt/opt_merge_init.ys @@ -75,3 +75,53 @@ EOT opt_merge select -assert-count 2 t:$dff + +design -reset +read_verilog -icells <<EOT +module top(input clk, i, (* init = 1'b0 *) output o, p); + \$dff #( + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) ffo ( + .CLK(clk), + .D(i), + .Q(o) + ); + \$dff #( + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) ffp ( + .CLK(clk), + .D(i), + .Q(p) + ); +endmodule +EOT + +opt_merge -keepdc +select -assert-count 1 t:$dff + +design -reset +read_verilog -icells <<EOT +module top(input clk, i, output o, p); + \$dff #( + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) ffo ( + .CLK(clk), + .D(i), + .Q(o) + ); + \$dff #( + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) ffp ( + .CLK(clk), + .D(i), + .Q(p) + ); +endmodule +EOT + +opt_merge -keepdc +select -assert-count 2 t:$dff |