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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-12 19:00:26 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-12 19:00:26 -0800 |
| commit | d0ee4cd88f1f966c194fdc60e47ef67944882afb (patch) | |
| tree | 9cd95cc7d2a3d25c8e460638f8ee51b1e613bde1 /tests | |
| parent | 01116f0f0a0ace0c676271904222932dd433aae1 (diff) | |
| download | yosys-d0ee4cd88f1f966c194fdc60e47ef67944882afb.tar.gz yosys-d0ee4cd88f1f966c194fdc60e47ef67944882afb.tar.bz2 yosys-d0ee4cd88f1f966c194fdc60e47ef67944882afb.zip | |
Remove extraneous synth_xilinx call
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/arch/xilinx/lutram.ys | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/tests/arch/xilinx/lutram.ys b/tests/arch/xilinx/lutram.ys index 36367eff1..a2ede75a5 100644 --- a/tests/arch/xilinx/lutram.ys +++ b/tests/arch/xilinx/lutram.ys @@ -62,7 +62,6 @@ read_verilog ../common/lutram.v hierarchy -top lutram_1w3r proc memory -nomap -synth_xilinx equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx memory opt -full @@ -83,7 +82,6 @@ read_verilog ../common/lutram.v hierarchy -top lutram_1w3r -chparam A_WIDTH 6 proc memory -nomap -synth_xilinx equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx memory opt -full |