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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-30 15:01:08 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-30 15:01:08 -0700 |
| commit | d508dc2906f27b088e9c1c40e7cf2f475e80c15b (patch) | |
| tree | 011f23d1db7e89cf19df081b3f4cad7aa726b789 /tests | |
| parent | 390cf34d0a8f815ea9828f9a455b36164f9d5607 (diff) | |
| download | yosys-d508dc2906f27b088e9c1c40e7cf2f475e80c15b.tar.gz yosys-d508dc2906f27b088e9c1c40e7cf2f475e80c15b.tar.bz2 yosys-d508dc2906f27b088e9c1c40e7cf2f475e80c15b.zip | |
Update test for ffM
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/xilinx/mul_unsigned.ys | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/tests/xilinx/mul_unsigned.ys b/tests/xilinx/mul_unsigned.ys index 72d1f37d7..30c034afe 100644 --- a/tests/xilinx/mul_unsigned.ys +++ b/tests/xilinx/mul_unsigned.ys @@ -7,5 +7,5 @@ cd mul_unsigned # Constrain all select calls below inside the top module stat select -assert-count 1 t:BUFG select -assert-count 1 t:DSP48E1 -select -assert-count 15 t:SRL16E -select -assert-none t:DSP48E1 t:SRL16E t:BUFG %% t:* %D +select -assert-count 30 t:FDRE +select -assert-none t:DSP48E1 t:FDRE t:BUFG %% t:* %D |