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| author | Clifford Wolf <clifford@clifford.at> | 2019-11-27 11:23:16 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-11-27 11:23:16 +0100 |
| commit | f43c0bd8ba2a736b86504725429e25df27a29ac0 (patch) | |
| tree | 4790cccdf4ed6c7eee7b90d8cfed6b941a53ac5f /tests | |
| parent | 95053d90109b707103bfbbd2927e6be36d69bca8 (diff) | |
| parent | fdcbda195b8806cc3f8fb98e80da55e756c285c4 (diff) | |
| download | yosys-f43c0bd8ba2a736b86504725429e25df27a29ac0.tar.gz yosys-f43c0bd8ba2a736b86504725429e25df27a29ac0.tar.bz2 yosys-f43c0bd8ba2a736b86504725429e25df27a29ac0.zip | |
Merge pull request #1534 from YosysHQ/mwk/opt_share-fix
opt_share: Fix handling of fine cells.
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/opt/bug1525.ys | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/tests/opt/bug1525.ys b/tests/opt/bug1525.ys new file mode 100644 index 000000000..972bc0ac7 --- /dev/null +++ b/tests/opt/bug1525.ys @@ -0,0 +1,13 @@ +read_verilog << EOF +module top(...); +input A1, A2, B, S; +output O; + +assign O = S ? (A1 & B) : (A2 & B); + +endmodule +EOF + +simplemap +opt_share +dump |