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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-18 12:40:21 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-18 12:40:21 -0700 |
| commit | f7dbfef7926e7239d83c8e9734f3d14edea46f80 (patch) | |
| tree | 97452d1922d426cf6cedab9f472c63fedb951a9b /tests | |
| parent | 44bf4ac35cf9f4fa81b8c9ae7f6e2f724e11934d (diff) | |
| parent | b66c99ece042e2dcda86ffa784e927eb910168a1 (diff) | |
| download | yosys-f7dbfef7926e7239d83c8e9734f3d14edea46f80.tar.gz yosys-f7dbfef7926e7239d83c8e9734f3d14edea46f80.tar.bz2 yosys-f7dbfef7926e7239d83c8e9734f3d14edea46f80.zip | |
Merge remote-tracking branch 'origin/master' into xc7dsp
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/various/peepopt.ys | 28 |
1 files changed, 26 insertions, 2 deletions
diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys index 886c8cd9d..6bca62e2b 100644 --- a/tests/various/peepopt.ys +++ b/tests/various/peepopt.ys @@ -16,7 +16,7 @@ select -assert-count 0 t:$shiftx t:* %D design -reset read_verilog <<EOT module peepopt_shiftmul_1 (output [7:0] y, input [2:0] w); -assign y = 1'b1 >> (w * (8'b110)); +assign y = 1'b1 >> (w * (3'b110)); endmodule EOT @@ -25,7 +25,31 @@ equiv_opt -assert peepopt design -load postopt clean select -assert-count 1 t:$shr -select -assert-count 0 t:$mul +select -assert-count 1 t:$mul +select -assert-count 0 t:$shr t:$mul %% t:* %D + +#################### + +design -reset +read_verilog <<EOT +module peepopt_shiftmul_2 (input [11:0] D, input [1:0] S, output [11:0] Y); + assign Y = D >> (S*3); +endmodule +EOT + +prep +design -save gold +peepopt +design -stash gate + +design -import gold -as gold peepopt_shiftmul_2 +design -import gate -as gate peepopt_shiftmul_2 + +miter -equiv -make_assert -make_outputs -ignore_gold_x -flatten gold gate miter +sat -show-public -enable_undef -prove-asserts miter +cd gate +select -assert-count 1 t:$shr +select -assert-count 1 t:$mul select -assert-count 0 t:$shr t:$mul %% t:* %D #################### |