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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2021-03-09 02:54:56 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-03-15 17:16:24 +0100 |
| commit | f965b3fa54eb38bf7f0246acc874087fc696f7f5 (patch) | |
| tree | db91d25dddaeefcc94daed1f784f3f4199bd8cf6 /tests | |
| parent | e178d0367a315213560514f827072595adfd4b4a (diff) | |
| download | yosys-f965b3fa54eb38bf7f0246acc874087fc696f7f5.tar.gz yosys-f965b3fa54eb38bf7f0246acc874087fc696f7f5.tar.bz2 yosys-f965b3fa54eb38bf7f0246acc874087fc696f7f5.zip | |
rtlil: Disallow 0-width chunks in SigSpec.
Among other problems, this also fixes equality comparisons between
SigSpec by enforcing a canonical form.
Also fix another minor issue with possible non-canonical SigSpec.
Fixes #2623.
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/opt/bug2623.ys | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/tests/opt/bug2623.ys b/tests/opt/bug2623.ys new file mode 100644 index 000000000..2ff23ea6f --- /dev/null +++ b/tests/opt/bug2623.ys @@ -0,0 +1,14 @@ +read_rtlil << EOT + +module \top + wire output 1 \a + wire width 0 $dummy + cell \abc \abc + connect \a \a + connect \b $dummy + end +end + +EOT + +opt_clean |