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author | Eddie Hung <eddie@fpgeh.com> | 2019-09-11 00:57:25 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-11 00:57:25 -0700 |
commit | fc7008671f26e60e37c1e901d8bffeb7bf49adda (patch) | |
tree | 7a0d941ab4713447b22b363b112362fea419d0fe /tests | |
parent | 6b23c7c2277e6a79dd547f42854bfe4fbe8d5565 (diff) | |
parent | edf90afd20046cb48273be8bc3da6ae2ea58d644 (diff) | |
download | yosys-fc7008671f26e60e37c1e901d8bffeb7bf49adda.tar.gz yosys-fc7008671f26e60e37c1e901d8bffeb7bf49adda.tar.bz2 yosys-fc7008671f26e60e37c1e901d8bffeb7bf49adda.zip |
Merge remote-tracking branch 'origin/eddie/peepopt_dffmuxext' into xc7dsp
Diffstat (limited to 'tests')
-rw-r--r-- | tests/various/peepopt.ys | 19 |
1 files changed, 18 insertions, 1 deletions
diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys index 33555264d..2a660d5c9 100644 --- a/tests/various/peepopt.ys +++ b/tests/various/peepopt.ys @@ -49,12 +49,29 @@ select -assert-count 0 t:* design -reset read_verilog <<EOT +module peepopt_dffmuxext_unsigned(input clk, ce, input [1:0] i, output reg [3:0] o); + always @(posedge clk) if (ce) o <= i; +endmodule +EOT + +proc +equiv_opt -assert peepopt +design -load postopt +clean +select -assert-count 1 t:$dff r:WIDTH=2 %i +select -assert-count 1 t:$mux r:WIDTH=2 %i +select -assert-count 0 t:$dff t:$mux %% t:* %D + +#################### + +design -reset +read_verilog <<EOT module peepopt_dffmuxext_signed(input clk, ce, input signed [1:0] i, output reg signed [3:0] o); always @(posedge clk) if (ce) o <= i; endmodule EOT -prep -nokeepdc +proc equiv_opt -assert peepopt design -load postopt clean |